1. Field
Exemplary embodiments of the present invention relate to a signal transmission/reception system.
2. Description of the Related Art
A plurality of circuits included in a semiconductor integrated circuit operates by exchanging signals with one another. These signals are transferred through transmission lines through which the plurality of circuits are electrically connected to one another. The transmission lines include metal lines and the like, and delay occurs in signals transferred through the transmission lines due to the resistance and capacitance of the transmission lines. In general, delay occurring due to resistance and capacitance is called an “RC delay.” The RC delay is increased as the resistance and capacitance of the transmission line is increased.
Meanwhile, packaging technology for a semiconductor integrated apparatus is being continuously advanced to keep up with requirements for miniaturization and high capacity. Thus, various technologies for manufacturing a stacked semiconductor apparatus capable of satisfying mounting efficiency as well as miniaturization and high capacity have been developed.
The stacked semiconductor apparatus can be fabricated using a method, in which individual semiconductor chips having different functions are stacked upon one another and the stacked chips are packaged at one time, or a method in which individually packaged semiconductor chips are stacked upon one another. In the stacked semiconductor apparatus, the individual semiconductor chips are electrically connected to one another through metal wires, through-silicon vias (TSVs) and the like.
Recently, a stacked semiconductor apparatus using through-silicon vias (TSVs) has been mainly fabricated. The stacked semiconductor apparatus using the through-silicon vias (TSVs) is fabricated by forming via holes through semiconductor chips, forming through electrodes (through-silicon vias, “TSVs”) by filling the via holes with conductive materials, and electrically connecting upper semiconductor chips to lower semiconductor chips through the through electrodes. The through-silicon via serves as a transmission line for transferring signals or power to each element of the stacked semiconductor apparatus.
However, the through-silicon via has high resistance and capacitance as compared with a metal line used as a transmission line. Therefore, RC delay is increased, resulting in the deterioration of signal transfer characteristics.
FIG. 1 is a diagram illustrating features occurring due to RC delay present in a transmission line.
A first signal S1 is input to a transmission line 101 through an input terminal IN of the transmission line 101, and a second signal S2 is output from the transmission line 101 through an output terminal OUT of the transmission line 101. A driver 102 drives the second signal S2 and transfers the second signal S2 to each element of a semiconductor integrated circuit. The second signal S2 is a signal modified from the first signal S1 due to an RC delay occurring in the transmission line 101. A third signal S3 is transferred to each element of the semiconductor integrated circuit by the driver 102.
Hereinafter, a description will be provided for the case in which the first signal S1 is a signal toggled at a regular interval.
The first signal S1 is changed to the second signal S2 by passing through the transmission line 101. The second signal S2 is transferred to each element of the semiconductor integrated circuit through the driver 102. For purposes of illustration, it is assumed that the driver 102 outputs ‘High’ when a level of the second signal S2 is higher than logic threshold T, and outputs ‘Low’ when the level of the second signal S2 is lower than the logic threshold T.
When an RC delay does not occur in the transmission line 101, the second signal S2 and the third signal S3 have substantially the same waveform as that of the first signal S1, except that the second signal S2 and the third signal S3 have a delayed phase as compared with the first signal S1. However, when the RC delay does occur in the transmission line 101 and the second signal S2 is modified as illustrated in FIG. 2, since the level of the second signal S2 does not exceed the logic threshold T of the driver 102, the third signal S3 has a waveform different from that of the first signal S1. Thus, a signal may not be normally transmitted due to the resistance and capacitance of the transmission line 101.
When the signal is not normally transmitted to each element of the semiconductor integrated circuit, an error may occur in the operation of the semiconductor integrated circuit. This feature becomes more pronounced as a toggle cycle of the first signal S1 becomes short (that is as an operation frequency is high). Since the transmission line 101 having capacitance is frequently charged/discharged as the toggle cycle becomes short, current consumption is also increased, where an increase in a voltage level of a signal loaded on the transmission line 101 means that the transmission line 101 is charged and a decrease in the voltage level of the signal loaded on the transmission line 101 means that the transmission line 101 is discharged.